Memories for storing data to be accessed by processors are known. Memories that are accessible by multiple processors are a convenient way of both storing data and passing data between the processors. In order for different processors to be able to access the same memory at the same time, memories with dual ports have been designed. These memories have two pairs of bit lines and two word lines for each bit cell, each port controlling a respective word line and pair of bit lines. Thus, a memory access at one port will activate one of the two word lines and this will cause the bit cells on that row to connect to the pair of bit lines associated with that port. A memory access to the other port will activate the other word line which will connect the other pair of bit lines to the bit cells on that row. In this way where different rows are accessed at a same time data from bit cells on the same column can be accessed via the respective bit lines.
Where different processors are accessing the same memory their clocks may not be aligned with each other and thus, the data accesses to the different ports may occur asynchronously. Whilst the use of multiport, for example dual port memories, may in many circumstances be advantageous they do give rise to certain difficulties.
Memory access collisions may occur if the same row is accessed from two ports at the same time. The processor logic will generally not allow the same cells to be accessed at the same time if one of the accesses is a write, however, different cells in the same row may be accessed and as access is controlled by the word line, both of the word lines to the one row may be turned on at the same time which will connect both sets of bit lines to the bit cells of that row. This means that if for example, one of the data accesses is a write, the value driven on the bit lines associated with that port will need to flip a bit cell which is also connected to another set of bit lines that are initially charged and thus, the parasitic capacitance of these bit lines will need to be overcome. This can cause a write failure.
US20009/0129194 assigned to ARM Limited of Cambridge UK, the entire contents of which are hereby incorporated by reference, discloses a multiport memory that provides control circuitry and override circuitry to identify read or write collisions and in response to detecting a collision actively drives both sets of bit lines with the value to be written thereby reducing the probability of a write failure occurring in response to a collision.